A chip is the most complicated thing humans make in quantity, and no country can make one alone. Walk the production line from sand to package and every step turns out to belong to somebody: an American design tool, a Dutch machine, a Japanese chemical, a Taiwanese fab, a Chinese test floor. Then look at who is racing to own more of it, and at what it costs to keep the lights on.
2026-09·10 views
Walk the line
Step 00 / 12
Step 00 · The object
The hardest thing we make by the million
A leading-edge processor is a sliver of silicon holding tens of billions of switches, each built at a scale where single atoms matter. A wafer of them passes through up to 1,400 process steps and spends about twelve weeks in the fab, fourteen to twenty for the most advanced processes.
No country does all of those steps. Each one belongs to somebody, and each one is a place where somebody else depends. Walk the line and find them.
Before any silicon is touched, a chip is drawn: billions of transistors arranged by electronic design automation (EDA) software and assembled from licensed blocks of core IP. The drawing is checked, simulated and checked again, because a mistake found after manufacturing costs months.
This is the most concentrated step on the line, and the least visible. Almost every advanced chip on earth is designed with tools from a handful of American companies.
US firms: 68% of value added in EDA & core IP (2022)
It really does start as quartz. Heated with carbon in an arc furnace, silica gives up its oxygen and leaves metallurgical-grade silicon, about 98% pure, which for a chip is filth.
Refining it into electronic-grade polysilicon pushes the purity to nine nines or better: fewer than one stray atom in a billion.
Step 03 · The crystal
One crystal, taller than a person
Pure is not enough; it has to be orderly. A seed crystal is dipped into molten silicon and drawn slowly upwards while both turn, and the melt freezes onto it in perfect registration with the seed’s lattice.
What comes out is a single unbroken crystal, an ingot, with no grain boundaries anywhere in it. This is the Czochralski method, and it has barely changed in principle since 1916.
Step 04 · The wafer
Sliced, then polished flatter than anything
A wire saw cuts the ingot into discs 300 mm across and three quarters of a millimetre thick. They are lapped, etched and polished until the surface is flat to within nanometres across the whole disc.
Few people have heard of the companies that do this, and the whole industry stands on them.
Leaders: Shin-Etsu and SUMCO (Japan), then GlobalWafers (Taiwan)
From here on the work alternates: add, then take away. Deposition grows films of insulator and metal on the wafer out of gas. Atomic layer deposition does it one atomic layer per cycle, which is exactly as slow as it sounds and exactly as precise as it needs to be.
The machines for this, and for nearly every other step, come from a short list of American, Japanese and European firms.
Tool makers by value added: US 47% · Japan 26% · EU 18%
The wafer spins at thousands of revolutions a minute while photoresist is dripped onto its centre, and the spin pulls it into a film of even thickness. Where light hits it, its chemistry flips. That is the whole trick of making a pattern.
It is also why lithography rooms are lit yellow: the resist is blind to long wavelengths and ruined by short ones.
Advanced resists come overwhelmingly from Japanese makers
Step 07 · Lithography
The machine only one company can build
Droplets of molten tin, about 25 microns across, leave a generator at 70 metres a second. A low-intensity laser pulse flattens each one into a pancake; a stronger pulse vaporises it into a plasma that glows at 13.5 nanometres, extreme ultraviolet. It happens 50,000 times a second.
Mirrors gather that light, bounce it off the patterned reticle and shrink the image onto the wafer. The machine that does it is the size of a bus, and every one in the world is built by ASML in the Netherlands.
Now the pattern becomes real. A plasma of reactive ions bombards the wafer and eats away whatever the resist left exposed. The ions arrive travelling straight down, so the trenches come out with vertical walls, not the rounded bowls a liquid would leave.
Deposit, pattern, etch, repeat, dozens of times over, each round adding another storey to a structure only an electron microscope can see.
Step 09 · Doping
Poison it, on purpose, with great precision
Pure silicon barely conducts. To make a transistor, it is contaminated deliberately: ions of boron, phosphorus or arsenic are accelerated, filtered by mass so that only the intended species gets through, and fired into the crystal.
A brief, violent anneal then heals the damage and locks the dopant atoms in place.
Step 10 · Wiring
Copper streets, stacked in storeys
The transistors are done; now they need connecting. Trenches are cut into insulator, filled with copper and polished flat, then the next level goes on top, linked to the one below by vias.
A modern logic chip carries a dozen or more of these levels. Unspooled, its wiring would run for kilometres.
Step 11 · Test & package
Find out how many of them actually work
Probes touch down on every die and test it in place. The wafer is diced, the failures thrown out, and the survivors packaged. More and more often, several chips and towers of memory are stacked into one module, which is how AI accelerators are built.
This is the step where the map changes. Assembly, test and packaging sits mostly in mainland China, Taiwan and Southeast Asia.
Assembly & test capacity: China 30% · Taiwan 28% · rest of world 20%
Behind all of it hums the part nobody photographs: pumps, chillers, air handlers turning the whole clean-room volume over again and again, ultrapure-water plants, and tool after tool drawing power around the clock. A leading-edge fab uses electricity like a city.
In 2024 TSMC alone used 25.55 billion kilowatt-hours. In 2020 its share of Taiwan’s electricity was about 6%, and it has been climbing since. It is now trimming its EUV tools’ peak power draw by as much as 44%, because every kilowatt on this line is one the grid has to find.
The line is global because nobody could afford to build all of it. The race is about changing that, or at least about not being the country that can be cut off. The United States appropriated $52 billion under its CHIPS Act, $39 billion of it in grants and loans for manufacturing. The EU’s Chips Act promises €43 billion of policy-driven investment by 2030. China registered the third phase of its national chip fund in May 2024, with 344 billion yuan.
Share of value added, by activity and region, 2022
Read across a row to see who owns a step of the line. No region leads more than a few rows, and the rows it leads are rarely the ones it depends on.
Design, EDA, equipment and materials are counted by where the company is headquartered; wafer fabrication and assembly by where the factory stands. Blank cells are under 1% or not shown in the source. “Weight” is each activity’s share of the industry’s total value added.
Share of global wafer capacity, 2022 and 2032 forecast
In 2022 every chip made on a process below 10 nm came out of Taiwan or South Korea. Subsidies and new fabs are forecast to spread the leading edge out over the next decade. They are not forecast to move most of it.
Installed capacity by fab location; fabs of 5,000+ wafer starts a month on 200 mm wafers or larger, R&D fabs excluded. Europe has no DRAM capacity in the source. 2032 is BCG’s forecast. Rows may not add to 100 because of rounding.
Most chip companies own no factory. They rent time at a foundry, and in the second quarter of 2026 almost three quarters of that business went to one company.
“Everyone else” is the remainder to 100% and includes Hua Hong, Tower, VIS, Nexchip and PSMC, the rest of the top ten. TSMC’s quarterly revenue was about US$40.2 billion.
Every leading-edge chip passes under one of these, and every one of them comes from a single company. China has received none: the Dutch government has not licensed their export there.
13.5 nmwavelength of the light
50,000tin droplets vaporised per second
~€350Mprice of one High-NA system
1company in the world that builds them
Systems on which ASML recognised sales in the year (2019: shipped). 2025 includes High-NA systems.
Chips cost electricity twice: once in the fab and again every second they run. Both bills are growing faster than the grids that pay them.
Two separate scales: the right-hand chart is roughly 25 times larger. 2030 values are projections (Greenpeace East Asia for chipmaking, the IEA’s base case for data centres); by the IEA’s count 945 TWh is slightly more than Japan uses today.
Three companies now make 2 nm-class chips in volume, and a fourth has a prototype. China’s best, made without EUV, is a generation or two behind, at a cost nobody publishes.
Node names are marketing, not measurements: no dimension of a “2 nm” transistor is 2 nm long, and one company’s node is not the same as another’s. SMIC’s dates are when outside analysts found the chips, not announcements.
